Lab 1
Introduction and Goals
The goal of this laboratory assignment is to familiarize you with the Chipyard simulation environment through a series of simple experiments. By modifying an existing instruction tracer script, you will collect instruction mix statistics and make architectural recommendations based on the results. You will conduct cycle-accurate simulations of the “Sodor” instructional cores. These cores were designed to demonstrate basic principles of core design.
This lab consists of two sections: a directed portion and an open-ended portion. Everyone will complete the directed portion in the same way, and grades will be assigned based on correctness. The open-ended portion will allow you to pursue more creative investigations, and your grade will be based on the effort you make to complete the task or the arguments you provide in support of your ideas.
While students are encouraged to discuss solutions to the lab assignments with each other, you must complete the directed portion of the lab yourself and submit your own lab report for these problems. For the open-ended portion of each lab, students must work in groups of two or three. Each group will turn in a single report for the open-ended portion of the lab. You may work with different groups on different lab assignments throughout the course.
Graded Items
All reports must be submitted on Gradescope. Please label each section of your results clearly. All directed items must be turned in for evaluation. Your group only needs to submit one of the problems in the open-ended portion.
DIRECTED
Part 1: recorded instruction mixes for each benchmark and answers
Part 2: 1-stage CPI analysis answers
Part 3: 5-stage CPI analysis answers
Part 4: data and the modified section of Chisel source code
Part 5: design problem answers
Lab Feedback (for both sections)
OPEN-ENDED
Option 1: recorded ratio, answers, and source code
Option 2: instruction definition, test code, worksheet, modified section of Chisel source code
Option 3: processor modification design
Option 4: design proposal and supporting data
We strongly recommend finishing the directed portion before moving on to the open-ended portion of the lab.
Acknowledgments
Many people have contributed to versions of this lab over the years. This lab is based on work by Yunsup Lee. It was originally developed for CS 152 at UC Berkeley by Christopher Celio and was heavily inspired by the previous set of CS 152 labs, which targeted the Simics emulators and were written by Henry Cook. This lab was made possible through the work of Jonathan Bachrach, who led the development of Chisel, and Andrew Waterman, Yunsup Lee, David Patterson, and Krste Asanović, who developed the RISC-V ISA.
