Introduction and Goals
The goal of this laboratory assignment is to study processor memory hierarchy design by experiment. You will run cycle-accurate RTL simulations of a RISC-V processor attached to a small, parameterizable data cache and a fixed-latency DRAM model, measure it with the cache’s own hardware counters, and reason about what the numbers say. In the directed portion you hold the capacity of the L1 data cache fixed and sweep its associativity; in the open-ended portion you reverse-engineer a mystery cache configuration, design a hardware prefetcher for a variety of access patterns, or co-design a cache and the kernel of a matrix transpose.
This lab consists of two sections: a directed portion and an open-ended portion. Everyone will do the directed portion the same way, and grades will be assigned based on correctness. The open-ended portion will allow you to pursue more creative investigations, and your grade will be based on the effort made to complete the task or the arguments you provide in support of your ideas.
While students are encouraged to discuss solutions to the lab assignments with each other, you must complete the directed portion of the lab yourself and submit your own lab report for these problems. For the open-ended portion of each lab, students must work in groups of two or three. Each group will turn in a single report for the open-ended portion of the lab.
Graded Items
All reports are to be submitted through Gradescope. Please label each section of the results clearly. The directed portion should be completed individually, and all directed items must be turned in for evaluation. The open-ended portion is worth 70% of the grade for this lab and should be completed in groups of 2-3. Your group only needs to submit one of the options in the Open-Ended Portion. Only one group member should submit to Gradescope, and the rest of the group members should be added to the submission.
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(Directed) Part 1 - L1 Data Cache Associativity Sweep: the counter table for the four design points, the miss-rate plot, and answers to the questions
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(Open-ended) Option 1 - Reverse-Engineering a Mystery Memory Subsystem: the table of four cache parameters, and for each one the experiment you ran, the measurements themselves, and the reasoning that takes you from the data to the parameter
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(Open-ended) Option 2 - Design Your Own Hardware Prefetcher: the results table of baseline vs. prefetched cycles, speedup and counters for all six kernels, the per-kernel analysis, and your six prefetcher sources
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(Open-ended) Option 3 - Co-Designing a Cache and a Kernel: your kernel and cache configuration at each of the three area budgets, the results table against the naive and cache-oblivious baselines, and your kernel source
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(Directed) Feedback: submitted through a Google Form
Each open-ended option has a detailed section on what materials should be submitted for the report. Make sure to read through that section to ensure you have included all the necessary materials in your submission.
Feedback Portion
In order to improve the labs for the next offering of this course, we would like your feedback. Unlike Lab 1, this is no longer part of your report: instead, fill out the Lab 2 feedback form. Every student should submit the form individually, including the questions about your team.
Feel free to write as much or as little as you prefer (a point will be deducted only if the form is left completely empty).
Acknowledgments
This lab was heavily inspired by the previous set of CS 152 labs developed by Henry Cook, Yunsup Lee, and Andrew Waterman, which targeted functional simulators such as Simics and Spike. More recent iterations of this lab, developed by Donggyu Kim, David Biancolin, and Albert Magyar, used FireSim to run FPGA-based simulations on Amazon EC2 F1. The Sodor cache subsystem that this version of the lab is built around was developed by the course staff.